1. Field of the Invention
The disclosure relates generally to methods and systems for debugging designs, and, more particularly to methods and systems for synchronously debugging designs of integrated circuits (ICs) described equivalently at different design levels, such as a register transfer level (RTL) and a gate level.
2. Description of the Related Art
Currently, IC designers mainly work at the RTL when designing complex digital systems, and then synthesize their designs into gate-level implementations with synthesizing tools. Although automated tools for translating designs at different design levels are provided, designers still need to spend a significant amount of time in gate-level implementations since some design issues can only be discovered and resolved at the gate level. For example, these design issues may include manual design changes, timing optimizations, post-synthesis debugging, and others. Due to these design issues, debugging and tracing signals between two different design levels have become a technological bottleneck in the chip design industry.
What is needed is an automatic debugging scheme for synchronously debugging a design described equivalently at different design levels, such as the RTL level and the gate level, so that designers can browse and trace the two design levels at the same time, thus significantly reducing the debugging time for complex designs.